Active pulse positioning modulator

ABSTRACT

An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser.No. 61/086,315, filed on Aug. 5, 2008, which is hereby incorporated byreference in its entirety for all intents and purposes. The presentinvention is related to U.S. Pat. No. 7,453,250 issued Nov. 18, 2008which is hereby incorporated by reference in its entirety for allintents and purposes.

BRIEF DESCRIPTION OF THE DRAWINGS

The benefits, features, and advantages of the present invention willbecome better understood with regard to the following description, andaccompanying drawings where:

FIG. 1 is a block diagram of an exemplary DC-DC buck converter employinga single-phase voltage mode controller implemented according to anexemplary embodiment;

FIG. 2 is a simplified block diagram of an exemplary embodiment of thesingle-phase voltage mode controller of FIG. 1 implemented with adual-edge modulation scheme using dual ramps according to an exemplaryembodiment;

FIG. 3 is a simplified schematic and block diagram of an exemplaryembodiment of the oscillator of FIG. 2;

FIG. 4 is a block diagram of an exemplary DC-DC buck converter employinga two-phase voltage mode controller implemented according to anexemplary embodiment;

FIG. 5 is a simplified block diagram of an exemplary embodiment of thetwo-phase voltage mode controller of FIG. 4 implemented using dual rampsignals according to an exemplary embodiment;

FIG. 6 is a simplified block diagram of the up ramp generator of FIG. 9according to an exemplary embodiment;

FIG. 7 is a simplified block diagram of an exemplary embodiment of anN-phase voltage mode controller implemented using dual ramp signalsaccording to an exemplary embodiment;

FIG. 8 is a simplified timing diagram generally illustrating operationof the dual-edge modulation scheme using dual ramps described for asingle channel or for each channel of a multiphase converter;

FIG. 9 is a timing diagram plotting a two channel scheme including adown ramp DR1 and a PWM1 signal for a first channel and a down ramp DR2and a PWM2 signal for a second channel;

FIG. 10 is a schematic and block diagram of a down ramp generatorimplemented according to an exemplary embodiment for an exemplarymultiphase adaptive pulse positioning (APP) system;

FIG. 11 is a simplified schematic and block diagram of a ramp timinggenerator according to an alternative embodiment of the down rampgenerator of FIG. 10 using a master ramp generator;

FIG. 12 is a simplified block diagram of an exemplary embodiment of avoltage mode APP controller implemented according to an APP schemeaccording to an exemplary embodiment;

FIGS. 13, 14 and 15 are timing diagrams illustrating operation of theAPP controller of FIG. 12 for various operating conditions;

FIG. 16 is a timing diagram illustrating operation of a 4-channel APPregulator using the down ramp generator of FIG. 10 and the APPcontroller of FIG. 12 according to an exemplary embodiment;

FIG. 17 is a schematic diagram of a speed up filter circuit according toan exemplary embodiment which replaces the filter circuit and combinerof FIG. 10;

FIGS. 18 and 19 are timing diagrams illustrating operation of a3-channel APP regulator using the down ramp generator of FIG. 10 withthe speed up filter circuit of FIG. 17, and further using the APPcontroller of FIG. 12 according to an exemplary embodiment.

DETAILED DESCRIPTION

The following description is presented to enable one of ordinary skillin the art to make and use the present invention as provided within thecontext of a particular application and its requirements. Variousmodifications to the preferred embodiment will, however, be apparent toone skilled in the art, and the general principles defined herein may beapplied to other embodiments. Therefore, the present invention is notintended to be limited to the particular embodiments shown and describedherein, but is to be accorded the widest scope consistent with theprinciples and novel features herein disclosed.

FIG. 1 is a block diagram of an exemplary DC-DC buck converter 500employing a single-phase voltage mode controller 501 implementedaccording to an exemplary embodiment. The controller 501 has a PWM pincoupled to an input of a driver circuit 503, which drives the gates ofelectronic switches Q1 and Q2 having controlled current paths coupledbetween an input voltage VIN and power ground (PGND). The switches Q1,Q2 are designated with Q reference numbers and schematically shown assimplified representations of field-effect transistors (FETs), where itis understood that the switches Q1, Q2 may be implemented as anysuitable electronic switching devices, such as N-channel devices,P-channel devices, metal-oxide semiconductor FETs (MOSFETs),bipolar-junction transistors (BJTs), insulated gate bipolar transistors(IGBTs), or any other electronic switch configuration as known to thoseskilled in the art. In this example, the drain of Q1 is coupled to VINand its source is coupled to a phase node PH, which is coupled to thedrain of Q2. The source of Q2 is coupled to PGND. A node and the signalit carries assume the same name unless otherwise specified. The PH nodeis coupled to one end of an output inductor L, having its other endcoupled to an output voltage node VO (developing an output signal VO).VO is filtered by the inductance L and a capacitor circuit RC1 which iscoupled across a load resistor RL between VO and PGND. The resistorwithin RC1 is a series resistance of the capacitor and minimized as muchas possible. VO is fed back through a resistor R1 to a feedback pin FBof the controller 501. Another resistor-capacitor circuit RC2 is coupledbetween the FB pin and a compensation pin COMP of the controller 501. Afrequency set resistor RFS is coupled between a frequency set pin FS ofthe controller 501 and signal ground (GND). As understood by thoseskilled in the art, Q1 is turned on while Q2 is off to couple VINthrough the inductor L to develop the output signal VO, then Q1 isturned off and Q2 turned on to couple L to GND, and this switchingprocess is repeated as controlled by the PWM output of the controller501. The frequency of the clock signal generally controlling the PWMcycles is programmable within a certain range as determined by theresistor RFS. The frequency set function is only one of many frequencydetermination methods, such as, for example, an internal referencesignal (current or voltage) or the like. An internal reference signalavoids the use of the external frequency set pin FS.

FIG. 2 is a simplified block diagram of an exemplary embodiment of thesingle-phase voltage mode controller 501 implemented with a dual-edgemodulation scheme using dual ramps according to an exemplary embodiment.The FB pin is provided to the inverting (−) input of an error amplifier(E/A) 601, receiving a reference voltage VREF at its non-inverting (+)input provided by a reference circuit 603. The COMP pin is coupled tothe output of the E/A 601, which is further coupled to the non-inverting(+) input of a first comparator 605 and to the inverting (−) input ofanother comparator 607. An FB pin develops an FB signal or voltageindicative of the voltage level of the output voltage VO. The E/A 601amplifies the difference between FB and VREF and provides acorresponding COMP signal or voltage on the COMP pin. Thus, the COMPsignal is indicative of the output voltage error, or the differencebetween the actual voltage level of VO and its reference voltage levelas reflected by VREF. It may also be said that COMP is responsive to atransient load current change so that COMP is indicative of transientchanges of the output load. The FS pin is coupled to an oscillatorcircuit 609, having a first output providing the down ramp signal DR tothe inverting input of the comparator 605 and a second output providingthe up ramp signal UR to the non-inverting input of the comparator 607.The output of comparator 605, generating a “set” signal CS, is providedto the set input S of an R-S flip-flop 611 and the output of comparator607, generating a “reset” signal CR, is provided to the reset input R ofthe R-S flip-flop 611. The Q output of the R-S flip-flop 611 generatesthe PWM signal provided to (and by) the PWM pin of the controller 501.The R-S flip-flop 611 operates as pulse control logic to control thestate of the PWM signal based on the outputs of the comparators 605 and607. The PWM signal is internally fed back to the oscillator circuit609.

FIG. 3 is a simplified schematic and block diagram of the oscillatorcircuit 609 according to an exemplary embodiment. The oscillator circuit609 includes a first ramp circuit 706 for generating the down rampsignal DR and a second ramp circuit 708 for generating the up rampsignal UR. For the first ramp circuit 706, a voltage source 701 providesthe V1 voltage to one terminal of a single-pole, single-throw (SPST)switch S1, having its other terminal coupled to a node 702 that developsthe DR signal provided to the comparator 605. Node 702 is coupled to oneend of a capacitor CP1 and to the input of a current sink IC1. The otherend of the capacitor CP1 and the output of the current sink IC1 are eachcoupled to GND. For the second ramp circuit 708, another voltage source703 provides the V2 voltage to one terminal of another SPST switch S2,having its other terminal coupled to a node 704 that develops the URsignal provided to the comparator 607. Node 704 is coupled to one end ofa capacitor CP2 and to the input of a current source IC2. The other endof the capacitor CP2 and the input of the current source IC2 are eachcoupled to GND. A timing control circuit 705 generates a first timingsignal T1 provided to a control input of the switch S1 and a secondtiming signal T2 provided to a control input of the switch S2. The CLKsignal, which is generated by an oscillator 707, is provided to thetiming control circuit 705 and has a frequency determined by theexternally-coupled resistor RFS as previously described. The PWM signalis provided to the timing control circuit 705 for controlling timing ofthe DR and UR ramp signals. In an alternative embodiment, the CS and CRsignals may be used instead of the PWM signal.

The timing control circuit 705 asserts the T1 signal high to closeswitch S1 to reset the DR signal to the V1 voltage level. The timingcontrol circuit 705 asserts the T1 signal low to open the switch S1, sothat the current sink IC1 discharges the capacitor CP1 to create thenegative-going ramp of the DR signal. In one embodiment, the timingcontrol circuit 705 keeps the T1 signal low until the next pulse of theCLK signal so that the DR signal continues to ramp down, similar toconventional leading edge modulation schemes, and then asserts the T1signal high to close the switch S1 to reset DR back to the V1 voltagelevel to start the next CLK cycle. In an alternative embodiment, thetiming control circuit 705 closes the switch S1 when the PWM signal goeshigh to reset the DR signal back to V1 earlier in the CLK cycle. If theDR signal resets prior to the next CLK pulse, then it is held until thenext pulse of CLK.

The timing control circuit 705 asserts the T2 signal high to closeswitch S2 to reset the UR signal to the V2 voltage level. The timingcontrol circuit 705 asserts the T2 signal low to open the switch S2, sothat the current source IC2 charges the capacitor CP2 to create thepositive-going ramp of the UR signal. The timing control circuit 705controls the switch S2 via the T2 signal based on the PWM signal (or theCS and CR signals). When the PWM signal is low, the timing controlcircuit 705 closes the switch S2 via the T2 signal to keep the UR signalat V2. When the PWM signal is asserted high, the timing control circuit705 opens the switch S2 via the T2 signal to allow IC2 to charge CP2 togenerate the rising ramp of the UR signal.

Operation of the oscillator circuit 609, as controlled by the timingcontrol circuit 705, is illustrated by the timing diagram of FIG. 8 andthe block diagram of FIG. 2. When the DR signal falls to the voltagelevel of the COMP signal, the CS signal is asserted high to set the R-Sflip-flop 611 which asserts the PWM signal high. The timing controlcircuit 705 opens the switch S2 to initiate the rising slope of the URsignal. When the UR signal rises to the voltage level of the COMPsignal, the CR signal is asserted high to reset the R-S flip-flop 611which pulls the PWM signal back low. The timing control circuit 705closes the switch S2 to reset the UR signal back to V2. The comparisonof the DR signal with the COMP signal triggers assertion of the PWMsignal, which in turn triggers the rising slope of the UR signal. The URsignal determines the duration of the PWM signal, which is pulled backlow when the UR signal rises to the level of the COMP signal.

The slew rate of the UR signal is proportional to any selectedcombination of the input voltage VIN, the voltage of the PH node, thevoltage across the output inductor L, or the peak, average, orinstantaneous current through the output inductor L. The VIN and/or PHvoltages may be directly fed to the controller 501 or indirectlydetermined through various sensing means. Many techniques are known forsensing the current of the output inductor L.

FIG. 4 is a block diagram of an exemplary DC-DC buck converter 800employing a two-phase voltage mode controller 801 implemented accordingto an exemplary embodiment. The DC-DC buck converter 800 is similar tothe DC-DC buck converter 500 in which similar components or devicesassume identical reference numerals. The two-phase voltage modecontroller 801 is similar to the single-phase voltage mode controller501 and includes the FS, FB and COMP pins. The controller 801, however,includes first and second PWM pins PWM1 and PWM2 for controlling firstand second phase circuits 802, 804 of the two-phase system. The PWM1 pinof the controller 801 is coupled to an input of a first driver circuit803 (DRIVER1) of the first phase circuit 802, where the first drivercircuit 803 drives the gates of electronic switches Q1 and Q2 (of thefirst phase circuit 802) having controlled current paths coupled betweenan input voltage VIN and PGND. The driver circuit 803 and the switchesQ1 and Q2 are configured and coupled to operate in substantially thesame manner as the driver circuit 503 and the switches Q1 and Q2 of theDC-DC buck converter 500. The PWM2 pin of the controller 801 is coupledto an input of a second driver circuit 805 (DRIVER2) of the second phasecircuit 804, where the second driver circuit 805 drives the gates ofelectronic switches Q3 and Q4 (of the second phase circuit 804) havingcontrolled current paths coupled between an input voltage VIN and PGND.The driver circuit 805 and the switches Q3 and Q4 are also configuredand coupled to operate in substantially the same manner as the drivercircuit 503 and the switches Q1 and Q2 of the DC-DC buck converter 500.For the DC-DC buck converter 800, however, the source of Q1 and thedrain of Q2 are coupled together at a first phase node PH1 and coupledto one end of a first output inductor L1 (of the first phase circuit802). Likewise, the source of Q3 and the drain of Q4 are coupledtogether at a second phase node PH2 and coupled to one end of a secondoutput inductor L2 (of the second phase circuit 804). The other ends ofthe output inductors L1 and L2 are coupled together at an output nodedeveloping the output signal VO.

The remaining portion of the DC-DC buck converter 800 is substantiallyidentical to the DC-DC buck converter 500. In particular, VO is coupledto a capacitor circuit RC1 which is coupled across the load resistor RLbetween VO and PGND. VO is fed back through a resistor R1 to thefeedback pin FB of the controller 801. Another resistor-capacitorcircuit RC2 is coupled between the FB pin and the compensation pin COMPof the controller 801. A frequency set resistor RFS is coupled between afrequency set pin FS of the controller 801 and GND. The frequency of theclock signal generally controlling the PWM cycles is programmable withina certain range as determined by the resistor RFS. As noted above,various other methods may be used for the frequency set function. Thespecific component values of RC1, RL, R1, RFS and RC2 may be modified asappropriate. As understood by those skilled in the art, each phaseoperates in substantially the same manner as described above for theDC-DC buck converter 500, except that the two phases are operated 180degrees out of phase with respect to each other. The current through theoutput inductor L1 is shown as a first phase current I1, the currentthrough the output inductor L2 is shown as a second phase current I2,and the total output current of both phases is shown as a total currentIT flowing to the output node developing the VO signal. The currentthrough the load resistor RL is shown as a load current IL.

FIG. 5 is a simplified block diagram of an exemplary embodiment of thetwo-phase voltage mode controller 801 implemented using dual rampsignals according to an exemplary embodiment. The FB pin is provided tothe inverting input of an error amplifier (E/A) 901, receiving areference voltage VREF at its non-inverting input provided by areference circuit 903. The COMP pin is coupled to the output of the E/A901 (providing the COMP signal), which is further coupled to thenon-inverting inputs of a first comparator 907 and another comparator917, and to the inputs of current balance circuits 913 and 923. The FSpin is coupled to an oscillator and down ramp generator circuit 905,having a first output providing a first down ramp signal DR1 to theinverting input of the comparator 907 and a second output providing asecond down ramp signal DR2 to the inverting input of the comparator917. The output of the current balance circuit 913 provides a firstadjusted compensation signal CMP1 which is provided to the invertinginput of another comparator 909. The output of the current balancecircuit 923 provides a second adjusted compensation signal CMP2 which isprovided to the inverting input of another comparator 919. The output ofcomparator 907, generating a first set or “start” signal CS1, isprovided to the set input Sofa first R-S flip-flop 911. The output ofcomparator 909, generating a first reset or “stop” signal CR1, isprovided to the reset input R of the R-S flip-flop 911. The output ofcomparator 917, generating a second set or start signal CS2, is providedto the set input S of a second R-S flip-flop 921. The output ofcomparator 919, generating a second reset or stop signal CR2, isprovided to the reset input R of the R-S flip-flop 921.

The Q output of the R-S flip-flop 911 generates the PWM1 signal providedto (and by) the PWM1 pin of the controller 801, and the Q output of theR-S flip-flop 921 generates the PWM2 signal provided to (and by) thePWM2 pin of the controller 801. The PWM1 and PWM2 signals are providedto respective inputs of a pulse adder 927, having an output providing aphase number or pulse count signal “N” to a first input of a first upramp generator 915, having a second input receiving the PWM1 signal. Theup ramp generator 915 has an output coupled to the non-inverting inputof the comparator 909 for providing a first up ramp signal UR1. The Nsignal and the PWM2 signal are provided to respective inputs of a secondup ramp generator 925, having an output coupled to the non-invertinginput of the comparator 919 for providing a second up ramp signal UR2.In the embodiment illustrated, N is an integer number determining thetotal number of PWM signals that are turned on at the same time (orrepresenting the total number of active phases). Thus, the pulse adder927 outputs N=0 when PWM1 and PWM2 are both low, N=1 when either one butnot both of the PWM1 and PWM2 signals is high, and N=2 when both of thePWM1 and PWM2 signals are high.

The current balance circuits 913 and 923 collectively form a currentbalance system in which each operates to adjust the COMP signal based onthe total current IT of both phases and the corresponding phase currentof the respective phase I1 or I2. In one embodiment, the output of thecurrent balance circuit 913 is CMP1=COMP+k*(I2−I1) for phase 1, where“k” is a constant gain factor, I1 is the current of phase 1 (throughoutput inductor L1), and the asterisk “*” denotes multiplication.Likewise, the output of the current balance circuit 923 isCMP2=COMP+k*(I1−I2) for phase 2, where I2 is the current of phase 2(through output inductor L2). The respective current signals may besensed using any of a number of methods known to those skilled in theart. In this embodiment, when I1 and I2 are equal to each other, thecurrent balance circuits 913 and 923 have no impact on the operation. Itis noted that offsetting COMP in this manner is only one of many methodsof inserting balance feedback. Another method, for example, isadjustment of the slopes of the up ramp signals, which provides a moreconstant balance gain as the input to output voltage ratio changes.

FIG. 6 is a simplified block diagram of the up ramp generator 915according to an exemplary embodiment. The up ramp generator 925 isconfigured in substantially the same manner and is not furtherdescribed. The N signal is provided to a gain circuit 1101 whichmultiplies N by a gain factor “g” and outputs the value N*g to a controlinput of a controlled current source 1103. The current source 1103 hasan input coupled to GND and an output coupled to a node 1105 developingthe up ramp signal UR1. Node 1105 is coupled to one end of a capacitorC1 and to one terminal of a SPST switch SW. The other end of thecapacitor C1 is coupled to GND and the second terminal of the switch SWis coupled to the positive terminal of a voltage source 1107 developingthe VMIN voltage. The negative terminal of the voltage source 1107 iscoupled to GND. The switch SW has an inverted control terminal receivingthe PWM1 signal.

In operation, when the PWM1 signal is low, the switch SW is closed andthe UR1 signal is pulled down to the voltage level VMIN. Recall in FIG.6 that when the PWM1 signal is low, the UR1 signal is reset back toVMIN. When the PWM1 signal is pulled high, it opens the switch SW, sothat the current source 1103 generates a charge current IC to charge thecapacitor C1. While the switch SW is opened, the voltage of UR1increases based on the magnitude of IC. The magnitude of IC is apredetermined nominal value multiplied by the factor N*g. For N=1, theslew rate of UR1 is m1 and when N=2, the slew rate of UR1 is m2 aspreviously described. In the embodiment illustrated, m2 is twice that ofm1. Although not shown, another, higher voltage supply may be includedand coupled to the node 1105 via a diode or the like to limit thevoltage level of UR1 to a predetermined maximum level.

The current balance circuits 913 and 923 operate to divide the loadcurrent as evenly as practical amongst the phases. The current balancecircuits receive signals that represent the current in each phase andappropriately filters and otherwise processes the input signals togenerate current balance signals which are proportional to the deviationof the current in each phase from the average current of all phases.These current balance signals are combined as an offset term in thecalculation of the difference between a fixed reference and the COMPsignal used to determine the duration of the time intervals for eachrespective phase. The effect of the current balance circuits is to driveall phase currents toward each other in a closed loop method. Because ofthe closed loop nature of the circuit, provided that all phases aretreated equally, the offsets can be handled in a bipolar manner or canbe truncated or offset to produce strictly a positive or a negativeoffset.

FIG. 7 is a simplified block diagram of an exemplary embodiment of anN-phase voltage mode controller 1200 implemented using dual ramp signalsaccording to an exemplary embodiment. The N-phase voltage modecontroller 1200 is similar in configuration and operation to thetwo-phase voltage mode controller 801 except generalized to control upto “N” phases in which N is any positive integer greater than 0 (and canbe used to control a single phase if desired). The controller 1200includes the FS, FB and COMP pins in a similar manner as the controller801. The controller 1200 includes an E/A 1201 (similar to the E/A 901)having its inverting input coupled to the FB pin and its non-invertinginput receiving a reference voltage VREF. VREF is provided by areference circuit 1203 (similar to the reference circuit 903). Theoutput of E/A 1201 provides the COMP signal which is further provided tothe COMP pin and to each of N PWM controllers 1207, individually labeledPWM1 controller, PWM2 controller, PWM3 controller, . . . , PWMNcontroller. The PWM controllers 1207 each have an output providing acorresponding one of N PWM signals PWM1-PWMN provided to correspondingpins PWM1-PWMN. The PWM1-PWMN signals are also provided to respectiveinputs of a pulse adder 1209, having an output providing the N phasenumber signal to each of the PWM controllers 1207. The pulse adder 1209operates in a similar manner as the pulse adder 927 except adding up toN simultaneously active PWM pulses. The oscillator and down rampgenerator circuit 905 is replaced with a similar oscillator and downramp generator circuit 1205 having an input coupled to the FS pin and Noutputs providing corresponding down ramp signals DR1, DR2, DR3, . . . ,DRN, where each down ramp signal DR1-DRN is provided to a correspondingone of the N PWM controllers 1207.

The generator circuit 1205 operates in a similar manner as the generatorcircuit 905 except that it separates the down ramp signals by theappropriate nominal phase angles depending upon the number of active orselected phases in operation. For example, for two phases the two downramp signals DR1 and DR2 are separated by 180 degrees (e.g., 0, 180),for four phases the four down ramp signals DR1, DR2, DR3 and DR4 areseparated by 90 degrees (e.g., 0, 90, 180, 270), for six phases the sixdown ramp signals DR1-DR6 are separated by 60 degrees (e.g., 0, 60, 120,180, 240, 320), and so on. Each PWM controller 1207 includes a currentbalance circuit (e.g., similar to 913) receiving the COMP signal andproviding a corresponding modified compensation signal, an up rampgenerator (e.g., similar to 915) having inputs receiving the N phasenumber signal and a corresponding PWM signal and an output providing acorresponding up ramp signal, a first comparator (e.g., similar to 907)comparing a corresponding down ramp signal with the COMP signal andproviding a set signal, a second comparator (e.g., similar to 909)comparing the corresponding modified compensation signal with thecorresponding up ramp signal and providing a reset signal, and PWM logic(e.g., similar to R-S flip-flop 911) receiving the set and reset signalsand providing the corresponding PWM signal. The slew rate of each upramp signal of each phase is adjusted by the total number of PWM pulsesignals that are high at the same time as determined by the N phasenumber signal provided by the pulse adder 1209.

FIG. 8 is a simplified timing diagram generally illustrating operationof the dual-edge modulation scheme using dual ramps described for asingle channel or for each channel of a multiphase converter. Anexemplary COMP signal is plotted with an exemplary down ramp signal DRand an exemplary up ramp signal UR and a PWM signal versus time. TheCOMP signal is simplified and shown as a non-varying horizontal linesignal, where it is understood that the COMP signal normally variesbased on operating conditions, such as with output voltage, loadcurrent, etc. DR repeatedly ramps down with constant slope from amaximum level to a minimum level and then resets back to the maximumlevel at a predetermined fixed frequency. Each time the DR signal fallsbelow COMP, such as shown at time t1, the UR signal is initiated andbegins ramping up from its minimum value and a pulse is initiated on thePWM signal. When the UR signal rises above COMP, such as shown at timet2, the PWM pulse is terminated and the UR signal is reset back to itsminimum value.

The dual-edge modulation scheme with dual ramps heretofore described asseveral benefits, particularly with respect to conventional leading edgeor trailing edge schemes. Each leading and trailing edge of each of thePWM pulses responds to load changes. For example, if COMP rises inresponse to increasing load (e.g., decrease in output voltage), itintersects DR sooner in the cycle thereby moving the PWM pulse ahead intime. Similarly, when COMP is higher, the up ramp UR ramps up higher andlonger before reaching COMP so that the PWM pulse is wider since itstays active longer. In response to decreased COMP, the PWM pulses tendto move to later in time per cycle and may become shorter in duration.The dual-edge modulation scheme with dual ramps is also referred to asan active pulse positioning (APP) scheme in which PWM pulses arerepositioned and re-sized based on operating conditions, such as outputvoltage, load current, etc.

Each down ramp signal per channel has a fixed frequency. In this manner,load transients that are at or near the set PWM frequency or harmoniesthereof can cause high current imbalance between the channels FIG. 9 isa timing diagram plotting a two channel scheme including a down ramp DR1and a PWM1 signal for a first channel and a down ramp DR2 and a PWM2signal for a second channel, and a COMP signal shown as a dotted line.DR1 is shown as a solid line whereas DR2 is shown as a dashed line andboth are superimposed on top of each other along with the COMP signal.The up ramp signals are not shown but operate in a similar manner perchannel as shown in FIG. 8. COMP is shown oscillating at or near thefrequency of each down ramp signal. The repetitive waveform on the COMPsignal keeps missing the peak of DR2 for each cycle so that PWM pulsesonly occur on the PWM1 signal as illustrated in FIG. 9, resulting in acurrent imbalance between the channels. Thus, pulses occur only on thefirst phase whereas no pulses occur on the second phase, and the phasesare activated out or order for one or more cycles. In one modified dualpulse scheme, pulses are inserted when the modulator misses pulses tocounteract this imbalance. The insertion of pulses in this manner maylead to chaotic behavior within the modulator, such as when the channels“fire” out of sequence. It is desirable to maintain a strict firingorder in a multiphase regulator system.

FIG. 10 is a schematic and block diagram of a down ramp generator 1000implemented according to an exemplary embodiment for an exemplarymultiphase adaptive pulse positioning (APP) system. The down rampgenerator 1000 generates down ramps as the leading edge ramp signals,where it is understood that positive-going or up ramps may be usedinstead as the leading edge ramp signals in alternative configurations.The COMP signal is provided to an input of a filter circuit 1001, havingan output providing a filtered compensation signal FCOMP to one input ofa combiner 1003, such as an adder or the like. A frequency set signal FSis provided to another input of the combiner 1003, which has an outputdeveloping an adjusted FS signal AFS. AFS is provided to a firstswitched pole of a switch SW1. The FS signal is provided on the FS pinor any other node providing frequency set information. The switch SW1 isshown as a single-pole, double-throw (SPDT) switch having a common polecoupled to a ramp control node RCTL developing a ramp control signalRCTL. The other switched pole of SW1 is coupled to ground and iscontrolled by a signal WAIT. A limiter diode 1005 has its anode coupledto node RCTL and its cathode coupled to a limiter circuit 1007. Thelimiter circuit 1007 limits the maximum voltage of RCTL such that whenRCTL rises to the maximum voltage forward biasing the limiter diode1005, the limiter circuit 1007 clamps the voltage of RCTL to the maximumvoltage. The RCTL node is coupled to the current control input of eachof a set of N current sinks 1008, in which “N” is an integer greaterthan zero (0) which determines the number of channels or phases of theAPP system. Each current sink 1008 is coupled between a correspondingone of N down ramp nodes VDR1, . . . , VDRN and ground and sinks acorresponding one of N currents IR1, . . . , IRN as controlled by RCTLfor the N channels. Each channel includes at least one capacitor 1002coupled between ground and at least one pole of a reset switch 1006,which selectively couples the other end of the capacitor 1002 to acorresponding one of the down ramp nodes VDR1-VDRN and another nodecoupled via a corresponding one of N resistors R1-RN to an upper rampvoltage VTOP. The resistors R1-RN limit inrush current when charging thecorresponding capacitors. Each down ramp node VDR1-VDRN is coupled to aninput of a corresponding one of N output buffers 1004, each having anoutput providing a corresponding one of N down ramp signals DR1, . . . ,DRN.

A resistor ladder 1009 includes a set of series-coupled resistors withintermediate nodes having one end coupled to the upper ramp voltage VTOPand another end coupled to a lower ramp voltage VBOT. A switch SW2selects one of the intermediate junctions of the resistor ladder 1009 toprovide a tap voltage VTAP to one input of a comparator 1011. In oneembodiment, VTAP is selected such that (VTOP−VTAP)=(VTOP−VBOT)/N tosynchronize the down ramp signals as further described below. VTAP isthus selected to be (N−1) (VTOP−VBOT)/N which is 1/Nth of the full rampvoltage swing VTOP-VBOT from the upper voltage VTOP. Another switch SW3selects one of the down ramp signals DR1-DRN for coupling to the otherinput of the comparator 1011, which has an output coupled to an input ofa ring counter and decoder circuit 1013. The ring counter and decodercircuit 1013 has an output coupled to a control input of the switch SW3for selecting one of the down ramp signals DR1-DRN. The ring counter anddecoder circuit 1013 has another set of outputs coupled to the controlinputs of the reset switches 1006. The ring counter and decoder circuit1013 has another set of outputs providing synchronization pulses oncorresponding N synchronization nodes SYNC1-SYNCN. Each channel mayinclude one capacitor 1002 which is switched by a corresponding resetswitch 1006 between VTOP and a corresponding down ramp node VDRx, inwhich “x” appended at the end of a signal name represents an index valuebetween 1 and N, inclusive, denoting a corresponding channel in anN-channel system. In an alternative embodiment to speed up reset, asshown, each channel includes two capacitors 1002 and each reset switch1006 is configured as a double-pole, double-throw (DPDT) switch whichalternatively couples one channel capacitor to VTOP and the other tocorresponding node VDRx. In this manner, while one channel capacitor ischarged to VTOP, the other is discharged by a corresponding current sink1008 decreasing VDRx for developing a corresponding ramp voltage DRx.

In operation, FS is selected to correspond to a nominal frequency levelFNOM which is adjusted by FCOMP. Each of the current sinks 1008 arecontrolled by the same signal RCTL so that each of the ramp voltages DRxramp down at the same rate at any given time. The rate of decrease, orthe slope, of the ramp signals is controlled by RCTL. Assuming firstthat FCOMP is zero, RCTL is set at FS so that each of the ramp signalsDRx oscillate at FNOM. The ring counter and decoder circuit 1013advances to the next channel, such as channel 1, controls the switch SW3to advance to the corresponding ramp voltage, DR1, switches thecorresponding reset switch 1006 for channel 1, and asserts acorresponding pulse on SYNC1. When switched, the capacitor 1002, whichis charged to VTOP, is coupled to VDR1, and is discharged by thecorresponding current sink 1008. Thus, VDR1 starts at VTOP and beginsdecreasing and the corresponding ramp signal DR1 ramps down from VTOPtowards VBOT. When DR1 decreases to VTAP, which is 1/Nth of the way downfrom VTOP to VBOT, the comparator 1011 switches and the ring counter anddecoder circuit 1013 switches to the next channel 2 and asserts a pulseon SYNC2. While DR1 continues ramping down, DR2 is reset back to VTOPand begins ramping down towards VBOT. When DR2 decreases to VTAP, thecomparator 1011 switches again and the ring counter and decoder circuit1013 switches to the next channel 3 (assuming at least 3 channels) and apulse is asserted on SYNC3. At this time, DR1 has dropped to 2/Nths ofthe way down from VTOP, DR2 has dropped to 1/Nth down, and DR3 is resetback to VTOP. While DR1 and DR2 continue ramping down, DR3 is reset backto VTOP and begins ramping down towards VBOT. Operation continues inthis manner to the Nth channel, and operation wraps back to the firstchannel in round-robin fashion.

Assuming only 3 channels, DR1 has dropped ⅔rds down and DR2 has dropped⅓rd down when DR3 is reset back to VTOP. When DR3 drops ⅓ of the wayfrom VTOP to VBOT, DR2 has dropped ⅔rds and DR1 has dropped to 3/3rds orall the way to VBOT and is reset back to VTOP. Operation continues in around-robin fashion between the 3 channels. In general, the down rampgenerator 1000 resets N down ramp signals (or any appropriate leadingedge ramp signal) in round-robin order so that the N ramp signals areseparated from each other by 1/Nth of the voltage range VTOP-VBOT. As aspecific example, suppose VTOP=3V, VBOT=2V and N=4 for a four channelsystem. Thus, the voltage range between VTOP and VBOT is 1V and 1/Nth ofthis voltage range is 0.25V. When a first ramp 1 resets back to 3V, asecond ramp 2 is at 2.75V, a third ramp 3 is at 2.5V, and a fourth ramp4 is 2.25V. When the first ramp 1 drops to 2.75V, ramp 2 has dropped to2.5V, ramp 3 has dropped to 2.25V, and ramp 4 drops to 2.0V and then isreset back to 3V.

Under steady state operating conditions, operation of the down rampgenerator 1000 is substantially similar to the down ramp generator usedin the dual-edge modulation scheme using dual ramps previouslydescribed. In non-steady state conditions, however, the filter circuit1001 responds to changes of COMP and adjusts FCOMP accordingly. In analternative embodiment, the output voltage may be monitored instead, ora combination of COMP and the output voltage VO. In one embodiment,FCOMP increases RCTL up to a maximum level or decreases RCTL down to aminimum level, and the slope of each of the ramp voltages DR1-DRN isadjusted accordingly. In one embodiment, the slopes may be decreased tozero; in another embodiment, the slopes may decrease to a predeterminedminimum slope value greater than zero. In one embodiment, thepredetermined minimum slope value corresponds to the target frequencylevel of operation. When the slopes of the ramp voltages DR1-DRN areincreased so that they ramp down at a faster rate, the frequency ofmodulator increases. Likewise, when the slopes of the ramp voltagesDR1-DRN are decreased so that they ramp down at a slower rate, thefrequency of modulator decreases. For example, an increase in loadcurrent causes a drop of the output voltage VO and a correspondingincrease of the COMP signal. FCOMP increases so that the combiner 1003increases RCTL above FS so that the slope of each of the ramp voltagesDR1-DRN increases by a corresponding amount. The increase of the downramp slopes increases the operating frequency of the down ramp generator1000. In this manner, the frequency of operation increases withincreased load to more quickly respond to the increase of the load. Thelimiter circuit 1007 clamps RCTL to a maximum level corresponding to amaximum frequency of operation FMAX. In one embodiment, FMAX correspondsto 3/2 of FNOM established by FS.

In one embodiment, the filter circuit 1001 includes a bandpass filter(not shown) to both filter out noise and set the AC response of thecurrent sinks 1008. In this manner, the down ramps change due to thedelta or change of load current rather than the steady state loadcurrent. The filter circuit 1001 may also include a deadband filter (notshown) so that small values of change, such as normal output ripple, donot affect the down ramp voltages. In one embodiment, the bandpassfilter is implemented with a high pass filter (HPF) (not shown) and aseparate low pass filter (LPF) (not shown) to collectively filter outundesired frequencies, along with the separate deadband filter. In oneembodiment, the HPF is set at TSW/20 (in which TSW is 1/FNOM) and theLPF is set to TSW/1000. In one embodiment, the filter circuit 1001allows FCOMP to be positive or negative so that RCTL is either increasedor decreased to increase or decrease the down ramp voltages DR1-DRNduring operation. In one embodiment, the slope of each of the down rampvoltages DR1-DRN increases or decreases but is not allowed to drop belowthe level established by FS, so that the frequency at any given time isat or above FNOM. An exception to this is a WAIT function which forceseach of the down ramps to at or near zero, as further described below.

As described further below, each channel includes circuitry whichmonitors a corresponding one of the SYNCx signals to maintain PWM pulseorder for each of the N channels. The SYNCx signal for a given channelarms that channel for the current cycle and a PWM pulse occurring duringthe cycle resets the channel. If a second SYNCx pulse is received for achannel before that channel is reset, meaning that a PWM pulse did notoccur during the entire PWM cycle for that channel, then that channelasserts the WAIT signal to initiated the WAIT mode in which all of thedown ramps are temporarily paused. When WAIT is asserted, SW1 groundsRCTL to turn off the current sinks 1008 for each of the N channels (orat least set them all to a relatively low level). This effectivelysuspends the ramp voltages to hold their corresponding voltage levels(slope of the ramp voltages DR1-DRN go to zero or near zero) until WAITis de-asserted. In one embodiment, the WAIT outputs of the channels arewired-OR'd together so that any channel that misses a pulsesimultaneously pauses all of the N channels. When the compensationsignal rises to a predetermined minimum voltage level, such as VBOT, apulse is asserted on the channel that initiated the WAIT mode and WAITis de-asserted low. When WAIT is de-asserted low, operation resumes andPWM pulse order is maintained.

FIG. 11 is a simplified schematic and block diagram of a ramp timinggenerator 1300 according to an alternative embodiment of the down rampgenerator 1000 using a master ramp generator 1301. The comparator 1011has one input coupled to VTAP in the same manner but has its other inputreceiving a master ramp voltage DRM from the master ramp generator 1301.Thus, the switch SW3 is eliminated so that timing is controlled insteadby the master ramp generator 1301 rather than the actual ramp voltagesDR1-DRN. The master ramp generator 1301 is configured in substantiallythe same manner as the channel ramp generators (including acorresponding current sink 1008, one or more channel capacitors 1002, areset switch 1006, etc.) and is controlled by the RCTL voltage. Theoutput of the comparator 1011 is coupled to control the reset switch1006 of the master ramp generator 1301. Operation of the down rampgenerator 1000 using the master ramp generator 1301 is substantially thesame. When DRM drops to VTAP, which is 1/Nth (VTOP−VBOT) from VTOP asbefore, the comparator 1011 switches and resets the master rampgenerator 1301 back to VTOP. In this manner, the master ramp generator1301 operates at a higher frequency in which DRM ramps down toVTOP−(VTOP−VBOT)/N and then resets back to VTOP for each cycle. Anadvantage of the ramp timing generator 1300 is that the input of thecomparator 1011 is not coupled to the actual ramp voltages DR1-DRNavoiding glitches or voltage anomalies on the ramp voltages DR1-DRNcaused by switching of the comparator 1011. DRM ramps from VTOP down toVTOP−1/N(VTOP−VBOT) and resets back to VTOP each cycle, whereas theregular ramp voltages DR1-DRN operate in the same manner previouslydescribed.

FIG. 12 is a simplified block diagram of an exemplary embodiment of avoltage mode APP controller 1400 implemented according to an APP schemeaccording to an exemplary embodiment. The APP controller 1400 may beused for a single-phase scheme or for each channel of a multiphaseregulator system. A comparator 1401 has inputs coupled to the commonpoles of a DPDT switch 1403 similar to the DPDT 1006 previouslydescribed. A first pair of switched poles of the DPDT switch 1403receive the COMP signal and a down ramp signal DRx, and a second pair ofswitched poles of the DPDT switch 1403 receive an adjusted compensationsignal CMPx and an up ramp signal URx. As previously noted, “x” appendedat the end of a signal name represents an index value between 1 and N,inclusive, denoting any one of the channels in an N-channel system. Theappended “x” notation may be ignored for a single-phase orsingle-channel system. The CMPx signal is an adjusted version of theCOMP signal in a similar manner as the CMP1 and CMP2 signals at theoutputs of the current balance circuits 913 and 923, respectively. Inone embodiment, COMP is modified by average output current for ringbackreduction and offset for direct current mode (DCM) of operation. URx isa corresponding up ramp signal for the channel. A two-input OR gate 1405has a first input receiving a signal PWMx, a second input receiving theWAIT signal, and an output provided to the control input of the DPDTswitch 1403. When PWMx and WAIT are both low, the output of the OR gate1405 is low so that the switch 1403 selects and provides the COMP andDRx signals to the non-inverting and inverting inputs, respectively, ofthe comparator 1401. When either one (or both) of the PWMx and WAITsignals is (are) high, the output of the OR gate 1405 is high so thatthe switch 1403 selects and provides the CMPx and URx signals to thenon-inverting and inverting inputs, respectively, of the comparator1401.

The output of the comparator 1401 provides a first trigger signal TRIG1to one input of a 4-input AND gate 1407 and to one inverted input of a2-input AND gate 1409 with inverted inputs. A SYNCx signal is providedto the input of a pulse generator 1411, having an output providing apulse signal PSYNC to an inverted input of the AND gate 1407 and to theset input of a D-type flip-flop (DFF) 1413. The pulse generator 1411asserts a momentary high pulse on the PSYNC signal for each rising edgeof SYNCx. The SYNCx signal is also provided to the clock input ofanother DFF 1415, which receives a logic one (“1”) at its D input andwhich provides the WAIT signal at its Q output. The inverted Q output(Q) of the DFF 1415 outputs an inverted wait signal WAITB, which isprovided to the input of a delay block 1417. The output of the delayblock 1417 is coupled to the clock input of the DFF 1413. In oneembodiment, the delay block 1417 inserts a delay for every rising edgeof WAITB. The inverted Q output of the DFF 1413 develops an ARMB signal,which is provided to a reset input of the DFF 1415 and to the input of apulse generator 1419. The output of the pulse generator 1419 providesanother trigger signal TRIG2 to the set input of an R-S flip-flop (RSFF)1421 and to the other inverted input of the AND gate 1409. The pulsegenerator 1419 operates in a similar manner as the pulse generator 1411in which it asserts a momentary high pulse on the TRIG2 signal for eachrising edge of ARMB. The output of the AND gate 1409 is provided to thereset input of the RSFF 1421, and the Q output of the RSFF 1421 providesthe PWMx signal. The inverted Q output of the RSFF 1421 provides aninverted PWMx signal, or PWMxB, which is provided to the input of adelay block 1423. The output of the delay block 1423 develops a triggerenable signal TEN, which is provided to another input of the AND gate1407. In one embodiment, the delay block 1423 inserts a delay for everyrising edge of PWMxB before asserting TEN. The output of the AND gate1407 is provided to the reset input of the DFF 1413. The D input of theDFF 1413 receives a logic one. A signal OK is provided to another inputof the AND gate 1407, in which OK indicates that the adjustedcompensation signal is greater than the corresponding up ramp signalindicating that it is ok to start a pulse on the PWM signal. The OKsignal is common to all channels in a multiphase regulator system.

The down ramp generator 1000 generates a down ramp signal for eachchannel including DRx, and a separate up ramp generator generates eachup ramp signal for each channel including URx. The down ramp generator1000 further generates a pulse on SYNCx just after DRx is reset high. Aseparate APP controller 1400 is provided for each channel, where “x”denotes the particular channel number as previously described. WhilePWMx and WAIT are both low, the comparator 1401 compares COMP with DRxand when either PWMx or WAIT is high, the comparator 1401 compares CMPxwith URx. In general, then DRx falls to the level of COMP, the PWMxsignal is asserted high and URx begins ramping up. The comparator 1401switches to compare URx with CMPx. When URx reaches CMPx, the PWMxsignal is asserted back low. If the PWMx signal is not asserted by thetime DRx resets high again for the next cycle, the APP controller 1400asserts the WAIT signal to suspend the DRx signal (and every other downramp signal). This typically occurs when COMP is less than the lowestvoltage of DRx. The DPDT switch 1403 switches so that the comparator1401 compares CMPx with URx, where URx remains at its lowest levelrather than ramping up. A PWMx pulse is initiated as soon as CMPx risesto the voltage of URx.

FIGS. 13, 14 and 15 are timing diagrams illustrating operation of theAPP controller 1400 for various operating conditions. In each timingdiagram, SYNCx is followed by DRx, COMP, and URx superimposed on top ofeach other, which is then followed by TRIG1, ARMB, TRIG2 and PWMx allplotted versus time. The timing diagrams are simplified in that CMPx isnot shown, and URx is shown relative to COMP rather than CMPx. CMPx isan adjusted compensation signal which generally follows or is roughlyequivalent to COMP so that the timing diagrams sufficiently illustrateoperation. FIG. 13 illustrates normal operating mode under steady stateload conditions. The DFF 1413 is initially in reset state so that ARMBis initially high holding the DFF 1415 in a reset state. SYNCx goes highjust after DRx is reset high at the beginning of the cycle. Although notshown in the timing diagrams, PSYNC pulses high in response to SYNCxgoing high, and then goes back low. The DFF 1413 is set so that ARMBgoes low in response to the pulse on PSYNC. While PSYNC is high, the ANDgate 1407 is temporarily blocked from resetting the DFF 1413. It isnoted that since ARMB is high when SYNCx goes high at the beginning ofthe cycle, the rising edge of SYNCx does not set the DFF 1415 since itis held in reset state, so that WAIT remains low. PWMx is initially low,so that the comparator 1401 compares DRx with COMP. When DRx ramps downto COMP at a time t1, the comparator 1401 asserts TRIG1 high. SincePSYNC is low, PWMxB is high and OK is high, the AND gate 1407 resets theDFF 1413 so that ARMB goes high. ARMB going high holds the DFF 1415 inreset state until the next cycle. TRIGx is pulsed high by the pulsegenerator 1419, which sets the RSFF 1421 high pulling PWMx high. WhileTRIG2 is pulsed high, the reset of the RSFF 1421 is blocked by the ANDgate 1409. PWMx going high switches the DPDT switch 1403 so that thecomparator 1401 is switched to compare URx with CMPx. While switchinginputs, the comparator 1401 might otherwise output a pulse due toswitching noise. The potential noise, however, is blocked by the ANDgate 1409 from prematurely ending the PWM pulse. TRIG2 goes back lowafter a short delay through the pulse generator 1419. When URx rises toCMPx at about time t2, the comparator 1401 asserts TRIG1 back low andthe AND gate 1409 resets the RSFF 1421 so that PWMx goes back low. PWMxgoing low changes back the DPDT switch 1403 so that comparator 1401 iscoupled to COMP and DRx again, thus causing the comparator 1401 to gohigh again. Operation continues in similar manner for each cycle duringnormal operation.

FIG. 14 illustrates the case in which a pulse on PWMx begin in a firstcycle of DRx and extends to a second and subsequent cycle. In this case,the PWMx signal goes high and URx begins ramping up as normal at abouttime t1, but towards the very end of the first DRx cycle. The pulse onPWMx extends through the next rising edge of SYNCx at about time t2,which is the point at which the DFF 1413 is set. The DFF 1413 is set asindicated by ARMB going low just after SYNCx goes high. Since TRIG1 ishigh (and OK is high and PSYNC is low), this might otherwise reset theDFF 1413 just after it was set thereby wasting a trigger while PWMx wasalready high, which would prevent a trigger later in the second DRxcycle. While PWMx remains high, PWMxB is low preventing the AND gate1407 from resetting the DFF 1413. TRIG1 goes low when URx reaches CMP1at subsequent time t3, which resets the RSFF 1421 pulling PWMx low andPWMxB high. After a short delay through the delay block 1423 at time t4,TEN goes high after TRIG1 went low preventing premature reset of the DFF1413. The delay of the delay block 1423 also sets how closely a pulse onPWMx can be retriggered after having ended. In one embodiment, the delayis TSW/20.

FIG. 15 illustrates the case in which DRx does not reach COMP beforeresetting such that a pulse on PWMx is not achieved during a full cycle.As shown in FIG. 15, SYNCx goes high while ARMB is still low at abouttime t1 indicating that there was no pulse on PWMx during the previouscycle. Since ARMB is still low at the rising edge of SYNCx, the DFF 1415gets set pulling WAIT high. The down ramp generator 1000 pauses the DRxsignal (and any other down ramp signals) and the DPDT switch 1403 isswitched so that the comparator 1403 monitors the URx signal comparedwith CMP1. The URx signal remains reset and low until the next pulse onPWMx, so that the comparator 1401 really compares CMP1 (or COMP) withthe minimum voltage level of URx. When CMP1 (or COMP) rises above URx atabout time t2, TRIG1 goes high, the AND gate 1407 resets the DFF 1413,ARMB goes high resetting the DFF 1415 so that WAIT is pulled back low,and a pulse is generated on TRIG2 setting the RSFF 1421 to initiate apulse on PWMx. The DRx signal (and any other down ramp signals) resumenormal operation. WAIT going low causes a high edge on the inverted Qoutput of the DFF 1415, which is delayed by the delay block 1417 andwhich then clocks the DFF 1413 pulling ARMB back low. In this manner, anormal PWMx pulse is enabled to occur later in the same cycle, such asshown at time t3.

FIG. 16 is a timing diagram illustrating operation of a 4-channel APPregulator using the down ramp generator 1000 and the APP controller 1400according to an exemplary embodiment. The timing diagram is separatedinto three graphs, including an upper graph plotting DR1-DR4 and COMPsuperimposed on top of each other, a middle graph plotting PWM1-PWM4 ontop of each other with slight offset to distinguish the individualpulses, and a lower graph plotting output voltage VO, all versus time.Again, only COMP is shown where it is understood that the CMP1-CMP4signals generally track COMP and are used for comparison withcorresponding up ramp UR1-UR4 signals, which are not shown. At a timet1, the COMP signal quickly spikes very high and VO drops quickly inresponse to a load condition, such as sudden increase of load current.Each of the PWM1-PWM4 signals pulse high at about the same time (in theorder PWM2, PWM3, PWM4, PWM1) with about the same pulse width durationin response to the spike of COMP. The filter circuit 1001 responds tothe sudden increase of COMP by increasing FCOMP and thus RCTL so thatthe slope of each of the down ramp signals DR1-DR4 increase. The pulseson the PWM1-PWM4 signals cause an increase of VO and a concomitantdecrease of COMP, which causes termination of the PWM pulses at abouttime t2. In response to the sudden decrease of COMP, the filter circuit1001 reduces RCTL so that the slopes of the ramp signals DR1-DR4decrease after time t2 while COMP falls to a relatively low level. It isnoted that in this case, the slope of DR1-DR4 decreases to less thanthat set by FS. At subsequent time t3, COMP begins rising and the slopesof DR1-DR4 increase accordingly. In this manner, changes of loadconditions are sensed by the filter circuit 1001 for adjusting theslopes of the down ramp signals to adjust the pulses on the PWM1-PWM4signals. The down ramp slopes are increased (or decreased) to adaptivelyreposition the pulses sooner (later) in time and to increase (decrease)operating frequency.

At subsequent time t4, COMP rises to DR2 causing a corresponding pulseon PWM2. It is noted that although COMP also crossed DR4 and DR1, PWMpulses had already occurred earlier in the same cycles for these downramp signals so that pulses do not occur again on PWM4 and PWM1. Atabout time t5, COMP rises to DR3 causing a pulse on PWM3. Subsequentlyat about time t6, COMP drops very quickly (large negative change involtage per time, or −dv/dt) and VO jumps higher very quickly, such asin response to a sudden decrease of output load condition. The slope ofeach of the down ramp signals DR1-DR4 decreases to zero or near zerowhile COMP is low for this embodiment. COMP begins rising again and theslopes of DR1-DR4 increase. Although COMP is rising, it stays below theminimum voltage level of the down ramps while the down ramp DR4 reachesits minimum level and resets back to its maximum level at about time t7without a pulse on PWM4. WAIT is asserted and the down ramp signalsDR1-DR4 are momentarily paused until a time t8 when COMP reaches theminimum level of the up ramp signals. It is noted that the slope ofDR1-DR4 are at or near zero after time t7 until subsequent time t8. Attime t8, COMP rises above the predetermined minimum voltage level sothat WAIT is de-asserted low. When WAIT is de-asserted, the down rampsDR1-DR4 resume normal down ramping, and a pulse occurs on PWM4. Later atabout time t9, a sudden increase in load causes another fast increase ofCOMP and corresponding pulses on the PMW1-PWM4 signals. It is noted thatPWM4 also includes a second pulse during the same cycle of DR4 betweentimes t7 and t9. It is appreciated that the wait function of the downramp signals and operation of the APP controller 1400 keeps properordering of pulses on the PWM1-PWM4 signals. Thus, even though twopulses occur on PWM2 within the same cycle of DR4 because of the waitmode, pulses occur on PWM1-PWM3 in between the pulses on PWM4.

FIG. 17 is a schematic diagram of a speed up filter circuit 1500according to an exemplary embodiment which replaces the filter circuit1000 and the combiner 1003 of FIG. 10. The speed up filter circuit 1500enables the slopes of the down ramp signals to increase and decrease butdoes not allow the slopes of the down ramp signals to decrease below thelevel set by FS. The COMP signal is provided to the anode of a diode1501, having a cathode coupled to a node 1502. A voltage source 1503referenced to ground develops a voltage VBOT at the anode of anotherdiode, having its cathode coupled to node 1502. Node 1502 is coupled toone end of a capacitor 1507, to an input of a current sink 1509, and tothe input of a buffer 1511. The other end of the capacitor 1507 and theoutput of the current sink 1509 are coupled to ground. The output of thebuffer 1511 is coupled to one end of a capacitor 1513, having its otherend coupled to a node 1514. Node 1514 is coupled to an input of acurrent sink 1515, to the anode of a diode 1517, and to the positiveterminal of a voltage source 1521 developing a threshold voltage VTH.The output of the current sink 1515 is coupled to ground and the cathodeof the diode 1517 is coupled to the positive terminal of a voltagesource 1519 developing a limit voltage VLIM. The negative terminal ofthe voltage source 1519 is coupled to ground. The negative terminal ofthe voltage source 1521 is coupled to one input of a multiplier 1523,having a second input receiving FS (or any other frequency set signal)and an output coupled to the anode of a diode 1525. FS (or any otherfrequency set signal) is provided to the anode of a diode 1527, and thecathodes of diodes 1525 and 1527 are coupled together at node 1528developing the adjusted FS signal AFS. FS may be a voltage or a currentsignal in various embodiments as understood by those skilled in the art.

In operation of the speed up filter circuit 1500, the greater of COMPand VBOT is provided on node 1502 so that excursions of COMP below VBOTare ignored. The capacitor 1507 and current sink 1509 collectivelyoperate as a peak detect circuit so that peak excursions of COMP aretemporarily held at the output of the buffer 1511. The peak value isapplied by the buffer 1511 to the capacitor 1513 and current sink 1515collectively operating as a high pass filter asserting a filtered COMPvoltage FCOMP on node 1514. The high pass filter function filters out DCor steady state conditions and passes changes of COMP as FCOMP. Also,FCOMP is limited to a maximum voltage level VLIM by the voltage source1519. In one embodiment, VLIM is a 3/2's limiter or the like whichlimits the voltage of node 1514 to correspond to an average switchingfrequency of 3/2 FNOM. FCOMP is reduced by VTH to ignore relativelysmall changes of COMP below a threshold level. The multiplier 1523multiplies FCOMP (or FCOMP−VTH) by FS (or any other frequency setsignal) and provides a signal (FCOMP−VTH)*FS at its output. The gain ofthe multiplier 1523 is greater than or equal to one (or its output isprevented from dropping below zero). The higher of (FCOMP−VTH)*FS and FSis asserted on node 1528 as AFS used as the ramp control signal RCTL forcontrolling the current sinks 1008 of the down ramp generator 1000. Inthis manner, AFS is adjusted by changes of COMP but does not decreasebelow the minimum level established by FS. It is noted that the currentsinks 1509 and 1515 may be made to track FS so that the filter functionstrack the switching frequency. Note also that VLIM may be dynamicallyadjusted by a circuit (not shown) that monitors, for instance, theaverage switching frequency.

FIG. 18 is a timing diagram illustrating operation of a 3-channel APPregulator using the down ramp generator 1000 with the speed up filtercircuit 1500, and further using the APP controller 1400 according to anexemplary embodiment. The timing diagram is separated into three graphs,including an upper graph plotting DR1-DR3 and COMP superimposed on topof each other, a middle graph plotting PWM1-PWM3 on top of each otherwith slight offset to distinguish the individual pulses, and a lowergraph plotting output voltage VO, all versus time. Again, only COMP isshown where it is understood that the CMP1-CMP3 signals generally trackCOMP. Also, the up ramp signals UR1-UR3 are not shown. Operation issimilar to that shown in FIG. 16 except that only 3 channels areimplemented and the speed up filter circuit 1500 controls slope changesof the down ramp signals DR1-DR3. Operation proceeds at steady stateuntil a sudden load decrease at about time t1 causing a sudden decreaseof the COMP signal. In this case, the slopes of the down ramp signalsDR1-DR3 do not decrease but maintain steady state operation based on FS.At time t2, COMP is increasing but has not risen to the minimum level ofthe up ramp signals and DR2 completes a cycle without a pulse on PWM2.Thus, beginning at time t2, the WAIT signal is asserted until time t3when COMP reaches the up ramp voltage (or other minimum voltage level)and a pulse is asserted on PWM2. The down ramps resume normal downramping after time t3 and COMP remains relatively stable. Operationcontinues normally until a subsequent time t4 when COMP rises suddenlyin response to a sudden increase in load. The down ramp slopes areincreased and the frequency of operation increases from time t4 to atime t5 when COMP drops to within normal operating range and the outputvoltage VO is stabilized.

FIG. 19 is a timing diagram plotting the same signals as FIG. 18focusing in on operation between times t4 and t5. As shown, at time t4COMP increases and the slopes and frequency of the down ramp signalsincrease until time t5. After time t5 a short wait is encountered due tothe deadtime timer function of the delay block 1423.

Although the present invention has been described in considerable detailwith reference to certain preferred versions thereof, other versions andvariations are possible and contemplated. For example, the ramps andcomparators can be inverted, the signals can be copied and offset forpurposes of realization, the control method can be mapped into anequivalent digital control scheme, etc. The present invention isapplicable to a number of synchronous and asynchronous switchingregulator topologies. Further, the polarities can be interchanged fornegative voltage regulators. Those skilled in the art should appreciatethat they can readily use the disclosed conception and specificembodiments as a basis for designing or modifying other structures forproviding out the same purposes of the present invention withoutdeparting from the spirit and scope of the invention as defined by thefollowing claims.

What is claimed is:
 1. An adaptive pulse positioning modulator forcontrolling a regulated output voltage, comprising: a sense circuitwhich provides a compensation signal indicative of output voltage error;a filter circuit having an input receiving said compensation signal andan output providing an adjust signal; a leading ramp circuit whichprovides a repetitive first leading edge ramp signal having a slope at anominal level when said compensation signal is steady state and whichadjusts said slope based on said adjust signal; a comparator circuitwhich provides a first start trigger signal when said first leading edgeramp signal reaches said compensation signal and which provides a firstend trigger signal when a first trailing edge ramp signal reaches saidcompensation signal; a trailing ramp circuit which initiates ramping ofsaid first trailing edge ramp signal when said first start triggersignal is provided; and pulse control logic which initiates each pulseon a first pulse-width modulation (PWM) signal when said first starttrigger signal is provided and which terminates each said pulse on saidfirst PWM signal when said first end trigger signal is provided.
 2. Theadaptive pulse positioning modulator of claim 1, wherein said sensecircuit comprises an error amplifier which provides said compensationsignal indicative of error of said output voltage.
 3. The adaptive pulsepositioning modulator of claim 1, wherein said leading ramp circuitcomprises a down ramp generator and wherein said trailing ramp circuitcomprises an up ramp generator.
 4. The adaptive pulse positioningmodulator of claim 1, wherein said filter circuit controls said adjustsignal to increase said slope in response to an increase of saidcompensation signal and to decrease said slope in response to a decreaseof said compensation signal.
 5. The adaptive pulse positioning modulatorof claim 4, wherein said filter circuit prevents said slope from fallingbelow a predetermined minimum level.
 6. The adaptive pulse positioningmodulator of claim 1, wherein said leading ramp circuit provides anumber N of repetitive leading edge ramp signals each having said slopeat said nominal level when said compensation signal is steady state andwhich adjusts said slope based on said adjust signal, wherein N is aninteger greater than one, wherein said leading ramp circuit ramps eachof said leading edge ramp signals within a voltage range from a firstvoltage to a second voltage and then resets each of said leading edgeramp signals back to said first voltage, and wherein said leading rampcircuit resets said N leading edge ramp signals in round-robin orderseparated by 1/Nth of said voltage range.
 7. The adaptive pulsepositioning modulator of claim 6, further comprising: said comparatorcircuit providing one of N start trigger signals when a correspondingone of said N leading edge ramp signals reaches said compensation signaland providing one of N end trigger signals when a corresponding one of Ntrailing edge ramp signals reaches said compensation signal; saidtrailing ramp circuit initiating ramping one of said N trailing edgeramp signals when a corresponding one of said N start trigger signals isprovided; said pulse control logic initiating each pulse on acorresponding one of N PWM signals when a corresponding one of said Nstart trigger signals is provided and terminating each pulse on saidcorresponding PWM signal when a corresponding one of said N end triggersignals is provided; and wait logic which pauses each of said N leadingedge ramp signals when any one of said N PWM signals is not providedbetween successive resets of a corresponding one of said N leading edgeramp signals.
 8. The adaptive pulse positioning modulator of claim 7,wherein said wait logic resumes ramping of each of said N leading edgeramp signals when said compensation signal rises to a predeterminedminimum level.
 9. The adaptive pulse positioning modulator of claim 8,wherein said pulse control logic maintains said round-robin order. 10.The adaptive pulse positioning modulator of claim 7, wherein said filtercircuit controls said adjust signal to change said slope in response toa change of said compensation signal and wherein said filter circuitprevents said slope from falling below a predetermined minimum levelexcept when said wait logic pauses each of said N leading edge rampsignals.
 11. A power converter for providing a regulated output voltage,comprising: a first phase circuit controlled by pulses on a first pulsewidth modulation (PWM) signal for converting an input voltage to theoutput voltage via a first inductor; a sense circuit which provides acompensation signal indicative of output voltage error; a filter circuithaving an input receiving said compensation signal and an outputproviding an adjust signal; and an adaptive pulse positioning modulator,comprising: a leading ramp circuit which provides a repetitive firstleading edge ramp signal having a slope at a nominal level when saidcompensation signal is steady state and which adjusts said slope basedon said adjust signal; a comparator circuit which provides a first starttrigger signal when said first leading edge ramp signal reaches saidcompensation signal and which provides a first end trigger signal when afirst trailing edge ramp signal reaches said compensation signal; atrailing ramp circuit which initiates ramping of said first trailingedge ramp signal when said first start trigger signal is provided; andpulse control logic which initiates each pulse on said first PWM signalwhen said first start trigger signal is provided and which terminateseach said pulse on said first PWM signal when said first end triggersignal is provided.
 12. The power converter of claim 11, wherein saidfilter circuit controls said adjust signal to increase said slope inresponse to an increase of said compensation signal and to decrease saidslope in response to a decrease of said compensation signal.
 13. Thepower converter of claim 12, wherein said filter circuit prevents saidslope from falling below a predetermined minimum level.
 14. The powerconverter of claim 11, further comprising: a number N of phase circuits,each controlled by pulses on a corresponding one of N PWM signals forconverting said input voltage to said output voltage via a correspondingone of N inductors, wherein N is an integer greater than one; andwherein said adaptive pulse positioning modulator comprises: saidleading ramp circuit providing N repetitive leading edge ramp signalseach having said slope at said nominal level when said compensationsignal is steady state and which adjusts said slope based on said adjustsignal, wherein said leading ramp circuit ramps each of said leadingedge ramp signals within a voltage range from a first voltage to asecond voltage and then resets each of said leading edge ramp signalsback to said first voltage, and wherein said leading ramp circuit resetssaid N leading edge ramp signals in round-robin order separated by 1/Nthof said voltage range; said comparator circuit providing one of N starttrigger signals when a corresponding one of said N leading edge rampsignals reaches said compensation signal and providing one of N endtrigger signals when a corresponding one of N trailing edge ramp signalsreaches said compensation signal; said trailing ramp circuit initiatingramping one of said N trailing edge ramp signals when a correspondingone of said N start trigger signals is provided; said pulse controllogic initiating each pulse on a corresponding one of N PWM signals whena corresponding one of said N start trigger signals is provided andterminating each pulse on said corresponding PWM signal when acorresponding one of said N end trigger signals is provided; and waitlogic which pauses each of said N leading edge ramp signals when any oneof said N PWM signals is not provided between successive resets of acorresponding one of said N leading edge ramp signals.
 15. The powerconverter of claim 14, wherein said wait logic resumes ramping of eachof said N leading edge ramp signals when said compensation signal risesto a predetermined minimum level.
 16. The power converter of claim 15,wherein said pulse control logic maintains said round-robin order.
 17. Amethod of controlling a DC-DC converter providing a regulated outputvoltage, comprising: providing a compensation signal indicative of theoutput voltage error; filtering the compensation signal and providing anadjust signal indicative of a changes of the compensation signal;providing a repetitive first leading edge ramp signal having a slope ata nominal level when the compensation signal is steady state; adjustingthe slope of the first leading edge ramp signal based on the adjustsignal; providing a first start trigger signal when the first leadingedge ramp signal reaches the compensation signal; providing a first endtrigger signal when a first trailing edge ramp signal reaches thecompensation signal; initiating ramping of said the trailing edge rampsignal when the first start trigger signal is provided; initiating eachpulse on a first pulse-width modulation (PWM) signal when the firststart trigger signal is provided and terminating each pulse on the firstPWM signal when the first end trigger signal is provided.
 18. The methodof claim 17, wherein said adjusting the slope of the first leading edgeramp signal based on the adjust signal comprises increasing the slope inresponse to an increase of the compensation signal and decreasing theslope in response to a decrease of the compensation signal.
 19. Themethod of claim 17, wherein said adjusting the slope of the firstleading edge ramp signal based on the adjust signal comprises changingthe slope in response to changes of the compensation signal whilepreventing the slope from falling below a predetermined minimum level.20. The method of claim 17, further comprising: said providing arepetitive first leading edge ramp signal comprising providing Nrepetitive leading edge ramp signals each having the slope at thenominal level when the compensation signal is steady state, wherein N isa positive integer greater than one; ramping each of the leading edgeramp signals within a voltage range from a first voltage to a secondvoltage; resetting each of the N leading edge ramp signals back to thefirst voltage after reaching the second voltage in round-robin order andseparated by 1/Nth of the voltage range; said adjusting comprisingadjusting the slope of each of the N leading edge ramp signals based onthe adjust signal; said providing a first start trigger signalcomprising providing one of N start trigger signals when a correspondingone of the N leading edge ramp signals reaches the compensation signaland providing one of N end trigger signals when a corresponding one of Ntrailing edge ramp signals reaches the compensation signal; saidinitiating ramping comprising initiating ramping one of the N trailingedge ramp signals when a corresponding one of the N start triggersignals is provided; said initiating each pulse comprising initiatingeach pulse on a corresponding one of N PWM signals when a correspondingone of the N start trigger signals is provided and terminating eachpulse on the corresponding PWM signal when a corresponding one of the Nend trigger signals is provided; and pausing each of the N leading edgeramp signals when any one of the N PWM signals is not provided betweensuccessive resets of a corresponding one of the N leading edge rampsignals.
 21. The method of claim 20, further comprising resuming rampingof each of the N leading edge ramp signals when the compensation signalrises to a predetermined minimum level.
 22. The method of claim 21,further comprising maintaining the round-robin ordering.
 23. An adaptivepulse positioning modulator, comprising: a sense circuit that provides acompensation signal indicative of output voltage error; a filter circuithaving an input receiving said compensation signal and an outputproviding an adjust signal that changes in response to output loadtransients; a leading ramp circuit that provides a repetitive leadingedge ramp signal that has a slope with a nominal level used to develop apulse-width modulation (PWM) signal at a steady state frequency level,and that adjusts said slope of said leading edge ramp signal based onsaid adjust signal to change a frequency level of said PWM signal inresponse to said output load transients; and a comparator circuit thatcompares said leading edge ramp signal with said compensation signal forinitiating pulses on said PWM signal, and that compares a trailing edgeramp signal with said compensation signal for terminating said pulses.24. The adaptive pulse positioning modulator of claim 23, wherein saidleading ramp circuit increases said slope of said leading edge rampsignal to increase said frequency level of said PWM signal in responseto an increase of output load, and wherein said leading ramp circuitdecreases said slope of said leading edge ramp signal to decrease saidfrequency level of said PWM signal in response to a decrease of outputload.
 25. An adaptive pulse positioning multiphase modulator,comprising: a sense circuit that provides a compensation signalindicative of output voltage error; a filter circuit having an inputreceiving said compensation signal and an output providing an adjustsignal that changes in response to output load transients; a dual rampcircuit that develops a plurality of synchronized leading edge rampsignals for a corresponding plurality of phases, wherein said pluralityof synchronized leading edge ramp signals each have a common slopehaving a nominal level for developing an operating frequency at a steadystate level, and wherein said dual ramp circuit adjusts said commonslope of each of said plurality of synchronized leading edge rampsignals based on said adjust signal to change said operation frequencyin response to said output load transients; and a comparator circuitthat compares each of said plurality of synchronized leading edge rampsignals with said compensation signal for initiating pulses on each of aplurality of pulse-width modulation (PWM) signals, and that comparessaid compensation signal with each of a plurality of trailing edge rampsignals for terminating said pulses of said plurality of PWM signals.26. The adaptive pulse positioning multiphase modulator of claim 25,further comprising wait logic that temporarily pauses each of saidplurality of synchronized leading edge ramp signals when a pulse doesnot occur on any one of said plurality of PWM signals during an entirecycle of a corresponding one of said plurality of synchronized leadingedge ramp signals.